The present invention relates to the packaging of semiconductor devices in general and, more specifically, to a helix substrate and a three-dimensional (3D) package having the same.
Recently, with the advances in integrated circuit (IC) technology, 3D package has been developed. 3D packaging involves either stacking two or more dies within a single package, or stacking and connecting completed packages. 3D packages offer significant size reductions compared to existing packages as they pack more circuitry per square centimeter of board space and per cubic centimeter of application space. In light of these and numerous other advantages, 3D packages are capturing an increasing share of the market for IC packages. However, prior 3D packages use stacked dies or comprise stacking and connecting completed packages to combine more functions in one unit. Thus, the number of Input/Output (I/O) contacts for electrical connection between dies in the package and an external device and the number of layers of the stacked-dies are both limited. Therefore, it would be desirable to be able to assemble a 3D package with more I/O contacts and more layers of stacked-dies.
Accordingly, it is an object of the present invention to provide a 3D package having more I/O contacts and more layers of stacked-dies and a method of assembling such a package to solve the above-mentioned short comings of existing 3D packages.